Fabrication method of semiconductor integrated circuit device

ABSTRACT

A fabrication method of a semiconductor integrated circuit device including polishing the entire area of an edge of a wafer, for example, by using three polishing drums in which a polishing drum polishes the upper surface of the edge of the water relatively, the polishing drum polishes the central portion of the edge of the wafer relatively and a polishing drum polishes the lower surface of the edge of the wafer relatively, thereby preventing occurrence of obstacles which cause defoliation of thin films on the edge of the wafer.

BACKGROUND OF THE INVENTION

[0001] This invention concerns a fabrication method of a semiconductorintegrated circuit device and, more in particular, it relates to atechnique effective to application for the fabrication method of asemiconductor integrated circuit device including fabrication steps tosemiconductor wafers.

[0002] The present inventors have made a search for the prior art inview of preventing occurrence of obstacles from edges of wafers.

[0003] For example, Japanese Published Unexamined Patent Application No.2000-68273 discloses a technique of polishing a metal film by a CMPmethod to form a pattern and then removing a metal film remained onedges of a device forming surface of a wafer by a wet etching method,laser or CMP method thereby preventing occurrence of obstacles from theedges.

[0004] Further, polishing apparatus for polishing edges of wafers aredisclosed, for example, in Japanese Published Unexamined PatentApplication Hei 11(1999)-104942, Japanese Published Unexamined PatentApplication Hei 11(1999)-90803, Japanese Published Unexamined PatentApplication Hei 11(1999)-48109, Japanese Published Unexamined PatentApplication Hei 11(1999)-33888, Japanese Published Unexamined PatentApplication Hei 10(1998)-328989, Japanese Published Unexamined PatentApplication Hei 10(1998)-309666, Japanese Published Unexamined PatentApplication Hei 10(1998)-296641, Japanese Published Unexamined PatentApplication Hei 4(1992)-34931 and Japanese Published Unexamined PatentApplication Sho 64(1989)-71656.

SUMMARY OF THE INVENTION

[0005] For decreasing the resistivity of wirings that constitute asemiconductor integrated circuit device, application of a damascenemethod using copper series materials (copper or copper alloys) forwiring materials have been proceeded. The damascene method comprisesforming grooves that form wirings in an insulative film, then depositinga conductor film for forming the wirings on the insulation film and inthe grooves for forming wirings, further removing unnecessary portionsof the conductor film, for example, by a chemical mechanical polishingmethod (CMP) thereby leaving the conductor film only in the grooves toform buried wirings in the groove for forming wirings. This method candecrease the size of the wirings compared with the size of the wiringsof usual structures and, particularly, reduce the fabrication size forcopper series materials for which fine fabrication by etching method isdifficult.

[0006] The present inventors have studied a method, in the step usingthe CMP method, of forming a pattern over the entire surface of asemiconductor wafer (hereinafter simply referred to as a wafer)containing regions not capable of obtaining semiconductor chips(hereinafter simply referred to as a chip) as a product. This is becauseuniformness of polishing by the CMP polishing tends to undergo theeffect depending on the presence or absence of the pattern formed to thewafer. Further, for shortening the time required for exposure totransfer the pattern, the regions not capable of obtaining thesemiconductor chips as the product are set to such a small area that theuniformness of polishing by the CMP method can be kept.

[0007] By the way, the yield of semiconductor integrated circuit devicessuch as DARM (Dynamic Random Access Memory) is greatly effectuated byobstacles deposited on wafers used for the production. Particularly,obstacles are formed frequently from edges of wafers.

[0008] In a wafer, while the device-forming surface capable of obtainingsemiconductor chips as the product is flat, edges thereof are in arounded state having an angle relative to the flat surface. The presentinventors have found that thin films are defoliated at the roundedportions to form a source for obstacles.

[0009] The mechanism for defoliation of the thin film is to beexplained, for example, in a case of STI (Shallow Trench Isolation)step.

[0010] At first, after forming a pad oxide film on the surface of awafer, a silicon nitride film is deposited on the pad oxide film.Successively, after patterning the silicon nitride film by dry etchingusing a photoresist film, the pad oxide film and the wafer are etched byusing the photoresist film and the remaining silicon nitride film as amask to form grooves in the wafer. Then, after forming a thin oxide filmto the inside of the grooves, a silicon oxide film is deposited over thewafer. Successively, after densifying the silicon oxide film, thesilicon oxide film is polished by the CMP method with the siliconnitride film being as a polishing end point to leave the silicon oxidefilm in the inside of the grooves.

[0011] By the way, as described above, while the device forming surfacein the wafer capable of obtaining the semiconductor chips is flat, edgesthereof are in a rounded state having an angle relative to the flatsurface. Therefore, portions above the patterned pad oxide film andsilicon nitride film at the edges are in a state as covered with thesilicon oxide film. While the pad oxide film and the silicon nitridefilm are removed after the step described above, the pad oxide film andthe silicon nitride film at the wafer edges are covered with the siliconoxide film, so that they are left not being removed.

[0012] Subsequently, after forming a well by implanting impurities intothe wafer, the silicon oxide film covering the pad oxide film and thesilicon nitride film of the wafer edges are removed by a cleaning stepof using an HF (hydrofluoric acid) cleaning solution, to expose the padoxide film and the silicon nitride film. In this case, the pad oxidefilm is etched and the silicon nitride film thereabove is defoliated toform obstacles. Further, in the succeeding steps, since steps such as HFcleaning are repeated, the pad oxide film is etched in each of the stepsand the silicon nitride film thereabove is defoliated to possibly formobstacles.

[0013] This invention intends to provide a technique for preventingoccurrence of obstacles from a wafer in a fabrication method of asemiconductor integrated circuit device.

[0014] These and other objects, as well as novel features of thisinvention will become apparent by reading the descriptions of thepresent specification in conjunction with the appended drawings.

[0015] Among the inventions disclosed in the present application, theoutline for typical ones is to be explained briefly below.

[0016] That is, this invention includes the steps of forming a firstinsulative film on the surface of a semiconductor wafer, removing thefirst insulative film on the edge of the semiconductor wafer, patterningthe first insulative film after the step of removing the firstinsulative film, and forming a second insulative film over thesemiconductor wafer including a portion above the first insulative filmafter patterning the first insulative film.

[0017] Further, this invention includes the steps of forming a firstinsulative film on the surface of a semiconductor wafer, a step ofpatterning the first insulative film, forming a second insulative filmover the semiconductor wafer including a portion above the firstinsulative film after patterning the first insulative film, mechanicallyand chemically polishing the surface of the second insulative film,thereby flattening the surface thereof, and polishing the secondinsulative film on the edges of the semiconductor wafer with the firstinsulative film being as a polishing end point.

[0018] Further, this invention includes the steps of forming a thirdinsulative film on the surface of a semiconductor wafer, a step ofpatterning the third insulative film, forming a first conductive filmabove the semiconductor wafer after patterning the third insulativefilm, removing the first conductive film on the edges of thesemiconductor wafer after forming the first conductive layer andpolishing the first conductive film with the surface of the thirdinsulative film above a region for obtaining semiconductor chips of thesemiconductor wafer being as a polishing end point.

[0019] Further, this invention intrudes steps of forming a thirdinsulative film above the surface of a semiconductor wafer, a step ofpatterning the third insulative film, forming a first conductive film onthe semiconductor wafer after patterning the third insulative film,polishing the first conductive film with the surface of the thirdinsulative film at a portion above a semiconductor chip obtaining regionbeing as a polishing end point and removing the first conductive film onthe edges of the semiconductor wafer after polishing the firstconductive film.

BRIEF DESCRIPTION OF THE DRAWINGS

[0020]FIG. 1 is a fragmentary cross sectional view showing an examplefor a fabrication method of a semiconductor integrated circuit device asa preferred embodiment according to this invention;

[0021]FIG. 2 is a fragmentary cross sectional view showing in anenlarged scale the vicinity of a device-forming surface of a wafer shownin FIG. 1;

[0022]FIG. 3 is a fragmentary cross sectional view during thefabricating step of the semiconductor integrated circuit devicesucceeding to FIG. 1;

[0023]FIG. 4 is a plan view for explaining a polishing step for edges ofa wafer using polishing drums;

[0024]FIG. 5 is a fragmentary cross sectional view for explaining theangle of contact between one of the polishing drums shown in FIG. 4 andthe edge of the wafer;

[0025]FIG. 6 is a fragmentary cross sectional view for explaining theangle of contact between one of the polishing drums shown in FIG. 4 andthe edge of the wafer;

[0026]FIG. 7 is a fragmentary cross sectional view for explaining theangle of contact between one of the polishing drums shown in FIG. 4 andthe edge of the wafer;

[0027]FIG. 8 is a fragmentary cross sectional view for explaining thedifference of the shape of an edge of a wafer;

[0028]FIG. 9 is a fragmentary cross sectional view for explaining thedifference of the shape of an edge of a wafer;

[0029]FIG. 10 is a fragmentary cross sectional view for explaining thedifference of a film deposition state of a thin film deposited on awafer;

[0030]FIG. 11 is a fragmentary cross sectional view for explaining thedifference of a film deposition state of a thin film deposited on awafer;

[0031]FIG. 12 is a fragmentary cross sectional view during thefabricating step of a semiconductor integrated circuit device succeedingto FIG. 3;

[0032]FIG. 13 is a fragmentary cross sectional view showing, in anenlarged scale, the vicinity of a device-forming surface of the wafershown in FIG. 12;

[0033]FIG. 14 is a plan view for explaining a chip region capable ofobtaining chips and a dummy exposure region at the periphery thereof;

[0034]FIG. 15 is a fragmentary cross sectional view during thefabricating step of a semiconductor integrated circuit device succeedingto FIG. 12;

[0035]FIG. 16 is a fragmentary cross sectional view during thefabricating step of a semiconductor integrated circuit device succeedingto FIG. 13;

[0036]FIG. 17 is a fragmentary cross sectional view during thefabricating step of a semiconductor integrated circuit device succeedingto FIG. 15;

[0037]FIG. 18 is a fragmentary cross sectional view during thefabricating step of a semiconductor integrated circuit device succeedingto FIG. 16;

[0038]FIG. 19 is a fragmentary cross sectional view during thefabricating step of a semiconductor integrated circuit device succeedingto FIG. 17;

[0039]FIG. 20 is a fragmentary cross sectional view during thefabricating step of a semiconductor integrated circuit device succeedingto FIG. 18;

[0040]FIG. 21 is a fragmentary cross sectional view during thefabricating step of a semiconductor integrated circuit device succeedingto FIG. 19;

[0041]FIG. 22 is a fragmentary cross sectional view during thefabricating step of a semiconductor integrated circuit device succeedingto FIG. 20;

[0042]FIG. 23 is a fragmentary cross sectional view during thefabricating step of a semiconductor integrated circuit device succeedingto FIG. 22;

[0043]FIG. 24 is a fragmentary cross sectional view during thefabricating step of a semiconductor integrated circuit device succeedingto FIG. 23;

[0044]FIG. 25 is a fragmentary cross sectional view during thefabricating step of a semiconductor integrated circuit device succeedingto FIG. 24;

[0045]FIG. 26 is a fragmentary cross sectional view during thefabricating step of a semiconductor integrated circuit device succeedingto FIG. 25;

[0046]FIG. 27 is a fragmentary cross sectional view during fabricationstep of a semiconductor integrated circuit as a preferred embodimentaccording to this invention;

[0047]FIG. 28 is a fragmentary cross sectional view during thefabricating step of a semiconductor integrated circuit device succeedingto FIG. 27;

[0048]FIG. 29 is a fragmentary cross sectional view during thefabricating step of a semiconductor integrated circuit device succeedingto FIG. 26;

[0049]FIG. 30 is a fragmentary cross sectional view during thefabricating step of a semiconductor integrated circuit device succeedingto FIG. 28;

[0050]FIG. 31 is a fragmentary cross sectional view during thefabricating step of a semiconductor integrated circuit device succeedingto FIG. 30;

[0051]FIG. 32 is a fragmentary cross sectional view during fabricationstep of a semiconductor integrated circuit as a preferred embodimentaccording to this invention;

[0052]FIG. 33 is a fragmentary cross sectional view during thefabricating step of a semiconductor integrated circuit device succeedingto FIG. 32;

[0053]FIG. 34 is a fragmentary cross sectional view during thefabricating step of a semiconductor integrated circuit device succeedingto FIG. 33;

[0054]FIG. 35 is a fragmentary cross sectional view during thefabricating step of a semiconductor integrated circuit device succeedingto FIG. 34;

[0055]FIG. 36 is a fragmentary cross sectional view showing an examplefor a fabrication method of a semiconductor integrated circuit device asanother embodiment according to this invention;

[0056]FIG. 37 is a fragmentary cross sectional view during thefabricating step of a semiconductor integrated circuit device succeedingto FIG. 36;

[0057]FIG. 38 is a fragmentary cross sectional view during thefabricating step of a semiconductor integrated circuit device succeedingto FIG. 37;

[0058]FIG. 39 is a fragmentary cross sectional view during thefabricating step of a semiconductor integrated circuit device succeedingto FIG. 38;

[0059]FIG. 40 is a fragmentary cross sectional view during thefabricating step of a semiconductor integrated circuit device succeedingto FIG. 39;

[0060]FIG. 41 is a fragmentary cross sectional view during thefabricating step of a semiconductor integrated circuit device succeedingto FIG. 40;

[0061]FIG. 42 is a fragmentary cross sectional view showing an examplefor a fabrication method of a semiconductor integrated circuit device asa further embodiment according to this invention;

[0062]FIG. 43 is a fragmentary cross sectional view during thefabricating step of a semiconductor integrated circuit device succeedingto FIG. 42;

[0063]FIG. 44 is a fragmentary cross sectional view showing an examplefor a fabrication method of a semiconductor integrated circuit device asa still further embodiment according to this invention;

[0064]FIG. 45 is a fragmentary cross sectional view showing in anenlarged scale, the vicinity of a device forming surface of the wafershown in FIG. 44;

[0065]FIG. 46 is a fragmentary cross sectional view during thefabricating step of a semiconductor integrated circuit device succeedingto FIG. 44;

[0066]FIG. 47 is a fragmentary cross sectional view during thefabricating step of a semiconductor integrated circuit device succeedingto FIG. 46; and

[0067]FIG. 48 is a fragmentary cross sectional view showing an examplefor a fabrication method of a semiconductor integrated circuit device asa still further embodiment according to this invention.

DETAILED DESCRIPTION OF PREFERRED EMBODIMENTS

[0068] Meanings for the terms used in the present specification are tobe explained before describing the invention specifically.

[0069] A wafer means for the a single crystal silicon substrate(generally, of a substantially planar disk-like shape), a sapphiresubstrate, a glass substrate and other insulative, semi-insulative orsemiconductive substrate, as well as composite substrates thereof.Further, semiconductor integrated circuit devices when referred to inthe present specification mean not only those prepared on asemiconductive or insulative substrate such as a silicon wafer and asapphire substrate but also those prepared on insulative a substratesuch as made of glass, for example, in TFT (Thin-Film-Transistor) andSTN (Super-Twisted-Nematic) liquid crystals unless otherwise specified.

[0070] A device forming surface means a main surface of a wafer on whicha disk pattern corresponding to plural chip regions is formed byphotolithography.

[0071] An edge of a wafer means a region at the outer periphery of thewafer having an angle relative to the planar main surface and the rearface of the wafer, also including regions from the outer end in theplanar main surface and rear face of the wafer to regions capable ofobtaining chips as a product in the present specification.

[0072] A transfer pattern means a pattern transferred by a mask on thewafer and, specifically, a resist pattern and a pattern on the waferformed actually by using a resist pattern as a mask.

[0073] The resist pattern means a film pattern formed by patterning alight sensitive resin film (resist film) by photolithography. Thepattern also includes a mere resist film with no openings at all in therelevant portion.

[0074] Mechanical and chemical polishing generally means for polishing asurface to be polished while bringing the surface into contact with apolishing pad made, for example, of a relatively soft cloth-like sheetmaterial while moving the surface relatively in both directions undersupply of a slurry. In this specification, it also includes a method ofpolishing by relatively moving a surface to be polished to the surfaceof a hard grinding wheel, as well as a method of using fixed abrasivegrains and a abrasive grain free CMP not using abrasive grains.

[0075] In the preferred embodiments to be described below, they areexplained being divided into plural sections or embodiments if it isnecessary for the sake of convenience. However, unless otherwisespecified, they are not irrelevant with each other but are in such arelation that one of them is a partial or entire modified example,details or supplementary explanation for others.

[0076] Further, when numbers of constituents (also including numbers ofcomponents, numerical values, amounts and ranges) are referred to, theyare not restricted to specified numbers but may be more than or lessthan the specified numbers unless otherwise specified or except for thecase where they are apparently restricted to the specified numbers inview of principle.

[0077] Further, in the following embodiments, the constituent elements(also including elemental steps) are not always essential unlessotherwise specified, or except for the case where they are consideredapparently essential.

[0078] In the same manner, when the shape and the positionalrelationship or the like of the constituent elements are referred to inthe following embodiments, they include also those substantially similarwith the shape and the positional relationship unless otherwisespecified, or except for the case where they are considered apparentlynot so in view of principle. This is also applicable to the numeralvalues and the ranges described above.

[0079] In the drawings used for the pretreated embodiments, a transferpattern formed in a region not capable of obtaining chips as a productin the wafer is hatched also in the plan view for the sake of making thedrawing easy to see.

[0080] Further, in the preferred embodiments, MISFET (Metal InsulatorSemiconductor Field Effect Transistor) typically representing fieldeffect transistors is simply referred to as MIS, a p-channel type MISFETas pMIS, and an n-channel type MISFET as nMIS.

[0081] Preferred embodiments of this invention are to be explained indetails with reference to the drawings. Throughout the drawings forexplaining the preferred embodiments, those components having identicalfunctions carry the same reference numerals, for which duplicatedescriptions are to be omitted.

EMBODIMENT 1

[0082] In Embodiment 1, this invention is applied, for example, to afabrication method of a semiconductor integrated circuit device in whichan nMISQn is formed in a p-well in a semiconductor substrate.

[0083]FIG. 1 and FIG. 2 are fragmentary cross sectional views of a wafer(semiconductor substrate) 1 of Embodiment 1. FIG. 1 shows, particularly,the vicinity of an edge of the wafer 1 and FIG. 2 shows, particularly,the vicinity of a device forming surface in the wafer 1 in an enlargedscale.

[0084] At first, as shown in FIG. 1 and FIG. 2, a wafer comprising asingle crystal silicon (semiconductor substrate) 1 having a specificresistivity of about 10 Ωcm is provided. FIG. 2 is a fragmentary crosssectional view showing, in an enlarged scale, the vicinity of a devicesurface in the wafer 1. In Embodiment 1, the wafer has a thickness ofabout 750 μm and an outer periphery in a rounded state of about 350 μmradius. Further, in Embodiment 1, the edge width X of the wafer 1 isabout 5 mm from the outer peripheral end of the wafer 1.

[0085] Successively, the wafer 1 is heat-treated at about 850° C., and athin silicon oxide film (pad oxide film) 2 of about 10 nm thickness(first insulative film) is formed on the surface and then a siliconnitride film 3 (first insulative film) of about 120 nm thickness isdeposited on the silicon oxide film by a CVD (Chemical Vapor Deposition)method. The silicon oxide film 2 is formed with an aim of relaxingstresses applied to the substrate, for example, upon densifyingshrink-fitting silicon nitride film buried in the device isolationgrooves in the succeeding step. Further, since the silicon nitride film3 is less oxidized, it is utilized as a mask for preventing oxidation onthe surface of the wafer 1 therebelow (active region).

[0086] Then, as shown in FIG. 3, the silicon oxide film 2 and thesilicon nitride film 3 on the edge of the wafer 1 are removed. This canprevent the silicon oxide film and the silicon nitride film 3 fromremaining on the edge of the wafer. That is, it can prevent defoliationof the silicon oxide film 2 and the silicon nitride film 3 in thesucceeding cleaning step, which are deposited again to the wafer 1 toreduce the yield of the semiconductor integrated circuit device ofEmbodiment 1. Further, the step of removing the silicon oxide film 2 andthe silicon nitride film 3 on the edge of the wafer 1 is adapted suchthat the end face S for the silicon oxide film 2 and the silicon nitridefilm 3 has an angle of about 5° C. to 75° C. relative to the deviceforming surface of the wafer 1 after the removing step. This can preventin the subsequent thin film deposition step that the coverage of thethin film is lowered from the surface S to the surface of the wafer 1.

[0087] The step of removing the silicon oxide film 2 and the siliconnitride film 3 is conducted by using plural polishing drums and, forexample, an embodiment of using three polishing drums 4A to 4C(polishing device) as shown in FIG. 4 can be exemplified. Use of theplural polishing drums facilitates polishing for the entire area of theedge of the wafer 1 and the time required for polishing can beshortened. Each of the polishing drums 4A to 4C is wound around at theperiphery thereof with a soft polishing pad, and polishing is conductedby supplying a slurry such as a colloidal silica, cerium oxide oraluminum oxide to the polishing surface.

[0088]FIG. 5 to FIG. 7 are, respectively, cross sectional views takenalong line A-A (refer to FIG. 4), line B-B (refer to FIG. 4) and lineC-C (refer to FIG. 4).

[0089] As shown in FIG. 5 to FIG. 7, the polishing drum 4A polishes theupper surface of the edge of the wafer 1 (device forming surface),relatively, the polishing drum 4B polishes a central portion of the edgeof the wafer 1 relatively, and the polishing drum 4C polishes the lowersurface (rear face) of the edge of the wafer relatively. Further, thepolishing drums 4A to 4C conduct polishing by rotation while contactingthe wafer 1 at angles of θ1 to θ3 different from each other.Accordingly, it is possible to remove the silicon oxide film 2 and thesilicon nitride film 3 over the entire area of the edge of the wafer 1.

[0090] The shape of the edge of the wafer 1 includes a shape in whichthe edge is in the shape of an arc, a so-called fully round type asshown in FIG. 8 or a shape in which the end of the edge is flat, aso-called top end flat type as shown in FIG. 9. In Embodiment 1, anglesθ1 to θ3 at which the polishing drums 4A to 4C are in contact with thewafer 1 respectively can be set properly in accordance with the shape ofthe edge of the wafer 1. Further, the angles θ1 to θ3 can be setproperly in accordance with the deposition state of the silicon oxidefilm 2 and the silicon nitride film 3 to be removed. That is, by usingthe polishing drums 4A to 4C in Embodiment 1, the silicon oxide film 2and the silicon nitride film 3 can be removed with respect to thevarious shapes of the edges of the wafer 1 as shown in FIG. 8 and FIG. 9over the entire region of the edge.

[0091] Further, for the polishing drums 4A to 4C, the number of rotationand the pressure in contact with the wafer 1 can be set properly tochange the polishing speed. That is, the optimal polishing speed of thepolishing drums 4A to 4C can be set in accordance with the shape of theedge of the wafer 1 as described above in accordance with the standardof the wafer 1 and the film deposition state of the silicon oxide film 2and the silicon nitride film 3.

[0092] Further, also in a case of removing other thin films deposited onthe edge of the wafer by using the polishing drums 4A to 4C in thesubsequent steps, the thin films can be removed for the entire edge areaof the wafer 1 by optionally setting the angles θ1 to θ3 and the optimalpolishing speed of the polishing drums 4A to 4C. In a case where a thinfilm T1 is formed only on the upper side (device forming surface) of thewafer 1 relatively as shown in FIG. 10, the angle can be, for example,as: θ1=150°, θ2=120°, θ3=60°. In this case, when the thin film to beremoved can be removed only by the polishing drums 4A and 4B, thepolishing drum 4C can be saved.

[0093] On the other hand, in a case where the thin film T1 is formedfrom the upper surface (device forming surface) to the vicinity of thelower surface (rear face) of the wafer 1, as shown in FIG. 11 or in acase where the film is formed over the entire surface of the wafer 1,the angle can be set, for example, as θ1=135°, η2=90, θ3=45°. The thinfilm T1 on the edge of the wafer 1 can be removed in a short time bysetting the angles θ1-θ3 as described above.

[0094] In Embodiment 1, while description is made to a method ofremoving the silicon oxide film 2 and the silicon nitride film 3 on theedge of the wafer 1 by using the polishing drums 4A to 4C, the siliconoxide film 2 and the silicon nitride film 3 may be removed also by a dryetching method or a wet etching method instead of the polishing drums 4Ato 4C.

[0095] Then, as shown in FIG. 12 and FIG. 13, after coating aphotoresist film 5 on the wafer 1, the photoresist film 5 is patternedby exposure using a mask. In this case, as shown in FIG. 14, thephotoresist film 5 is patterned also in a dummy exposure region (hatchedarea) A2 at the periphery of a chip region A1 capable of obtainingchips. This is done for improving the uniformity of polishing in thesubsequent polishing step by the CMP method.

[0096] Then, as shown in FIG. 15 and FIG. 16, the silicon nitride film 3and the silicon oxide film 2 in the device isolation region are removedby dry etching using the photoresist film 5 as a mask. Successively,grooves 6 each of about 350 nm depth are formed to the wafer at thedevice isolation region by dry etching using the silicon nitride film 3as a mask.

[0097] Then, as shown in FIG. 17 and FIG. 18, for removing damagedlayers formed on the inner wall of the grooves 6 by etching, the wafer 1is heat treated at about 1000° C. to form a silicon oxide film 7 ofabout 10 nm thickness on the inner wall of the grooves 6. Successively,a silicon oxide film 8 (second insulative film) of about 380 nmthickness is deposited on the wafer 1 by a CVD method and then the wafer1 is heat treated to densify (sinter) the silicon oxide film 8 in orderto improve the film quality of the silicon oxide film 8.

[0098] Then, as shown in FIG. 19 and FIG. 20, the silicon oxide film 8is polished by a CMP method using the silicon nitride film 3 as astopper to leave the film in the inside of the grooves 6 thereby formingdevice isolation grooves planarized at the surface. Then, as shown inFIG. 21 and FIG. 22, the silicon nitride film 3 and the silicon oxidefilm 2 remaining on the active region of the wafer 1 are removed by wetetching using hot phosphoric acid. Since the silicon nitride film 3 andthe silicon oxide film 2 on the edge of the wafer 1 were alreadyremoved, the silicon nitride film 3 and the silicon oxide film 2 coveredwith the silicon oxide film 8 are not present on the edge. That is, itis possible to prevent, in the subsequent cleaning step that the siliconnitride film 3 and the silicon oxide film 2 are defoliated to formobstacles.

[0099] Then, as shown in FIG. 23, the wafer 1 is applied with a heattreatment to form a thin silicon oxide film (not illustrated) as a padoxide film upon ion implantation to the main surface of the wafer 1.Successively, n-impurities, for example, B (boron) are ion implantedinto a region forming nMIS of the wafer 1 to form a p-well 9. Afterforming the p-well 9, the silicon oxide film used for the ionimplantation step is removed by using an HF (fluoric acid) type cleaningsolution. In this case, since the surface of the silicon oxide film 8 isalso wet etched, the surface height of the silicon oxide film 8 and thesurface height of the wafer 1 in a region formed with the p-well 9 aresubstantially identical.

[0100] Then, as shown in FIG. 24, the wafer 1 is wet oxidized to form aclean gate oxide film 10 of about 3.5 nm thickness to the surface of thep-well 9. Successively, non-doped polycrystal silicon film of about 90to 100 nm thickness is deposited by a CVD method above the wafer 1.Successively, P (phosphorus) for example, are ion implanted into thenon-doped polycrystal silicon film in the upper portion of the p-well 9to form an n-polycrystal silicon film. Further, a silicon oxide film isdeposited on the surface of the n-polycrystal silicon film, therebyforming a stacked film, the stacked film is etched by using aphotoresist film patterned by lithography as a mask, to form a gateelectrode 11 and a cap insulative film 12. A high melting metal silicidefilm such as WSi_(x), MOSi_(x), TiSi_(x), TaSi_(x) or CoSi_(x) may bestacked over the gate electrode 11. The cap insulative film 12 can beformed, for example, by a CVD method.

[0101] Successively, after removing the photoresist film used for thefabrication of the gate electrode 11, n-type impurities, for example, Pare ion implanted to the p-well 9 to form an n⁻-type semiconductorregions 13 on both sides of the gate electrode 11.

[0102] Successively, a silicon oxide film of about 100 nm thickness isdeposited over the wafer 1 by a CVD method and the silicon oxide film isetched anisotropically by using reactive ion etching (RIE) to form sidewall spacers 14 on both sides of the gate electrode 11 of the nMIS.Successively, n-impurities, for example, As (arsenic) are ion implantedto p-well 9 to form an n⁺-type semiconductor region 15 (source·drain) ofnMIS. Thus, a source and drain region of an LDD (Lightly Doped Drain)structure is formed to nMISQn to complete nMISQn.

[0103] Then, as shown in FIG. 25, a silicon oxide film 16 is depositedabove the wafer by a CVD method. Subsequently, the silicon oxide film 16deposited on the edge of the wafer 1 may be removed by polishing theedge of the wafer using the polishing drum is 4A to 4C (refer to FIG. 4to FIG. 7). This can eliminate the worry that the silicon oxide film 16is defoliated on the edge of the wafer 1. That is, it is possible toprevent that the defoliated silicon oxide film 16 forms obstacles tolower the yield of the semiconductor integrated circuit device ofEmbodiment 1.

[0104] Successively, the surface of the silicon oxide film 16 isplanarized by polishing, for example, by a CMP method. Further,connection holes 17 are apertured in the oxide silicon film 16 above then⁺-type semiconductor region 15 of the main surface of the wafer 1 byusing photolithography. The step of removing the silicon oxide film 16on the edge of the wafer 1 may be conducted after the step ofplanarizing the surface of the silicon oxide film 16 or after the stepof aperturing the connection holes 17.

[0105] Then, a barrier conductor film 18A made, for example, of titaniumnitride is formed over the wafer 1 by a sputtering method and, further,a conductive film 18B, made of for example, of tungsten is deposited bya CVD method. Successively, the barrier conductor film 18A and theconductive film 18G on the silicon oxide film 6 other than theconnection holes 17 are removed, for example, by a CMP method to formplugs 18.

[0106] Then, as shown in FIG. 26, a silicon nitride film is depositedabove the wafer 1, for example, by a plasma CVD method to form anetching stopper film 19 (third insulative film) of about 100 nmthickness. The etching stopper film 19 is formed for avoiding, uponforming grooves or holes for forming wirings in the insulative filmthereabove, to give damages to the lower layers by excessive digging ordeteriorate the fabrication dimensional accuracy.

[0107] Successively, a fluorine-added SiOF (silicon oxide) film isdeposited on the surface of the etching stopper 19 by a CVD method todeposit an insulative film 20 (third insulative film) of about 400 nmthickness. In a case of using the SiOF film for the insulative film 20,since the SiOF film is a low dielectric film, overall dielectricconstant of the wirings for the semiconductor integrated circuit devicecan be lowered to improve wiring delay. FIG. 27 shows the vicinity ofthe edge of the wafer 1 in this step. In FIG. 27, for easy understandingof the subsequent step of depositing the insulation film and the step offorming the wiring groove, other components than the wafer 1, thesilicon oxide film 16, the insulative film 20 and the wiring grooves 21are not illustrated.

[0108] Then, in the same manner as for the silicon oxide film 16, theedge of the wafer 1 may be polished by using the polishing drums 4A to4C (refer to FIG. 4 to FIG. 7), thereby removing etching stopper 19 andthe insulative film 20 deposited on the edge of the wafer 1. This caneliminate the possibility that the etching stopper 19 and the insulativefilm 20 are defoliated on the edge of the wafer 1. That is, it ispossible to prevent that the defoliated etching stopper film 19 and theinsulative film 20 form obstacles to lower the yield of thesemiconductor integrated circuit device of Embodiment 1.

[0109] Successively, as shown in FIG. 26 described above, the surface ofthe insulative film 20 is planarized, for example, by polishing with aCMP method. Subsequently, the etching stopper film 19 and the insulativefilm 20 are fabricated by using photolithography and dry etching to formwiring grooves 21. The step of removing the etching stopper 19 and theinsulative film 20 deposited on the edge of the wafer 1 may be conductedsubsequent to the step of planarizing the surface of the insulative film20 or subsequent to the step of forming the wiring grooves 21.

[0110] Successively, for removing the reaction layer on the surface ofthe plug 18 exposed at the bottom of the wiring grooves 21, the surfaceof the wafer 1 is treated in an Ar (argon) atmosphere. The amount ofsputter etching in this step is, for example, of about 20 Å to 180 Å,preferably, about 100 Å being converted as a p-TEOS (PlasmaTetre-Ethyl-Ortho-Silicate) film. Embodiment 1 shows a case of removingthe reaction layer on the surface of the plug 18 by sputter etching inthe argon atmosphere as an example, but so long as the reaction layercan be removed sufficiently by an annealing treatment, for example, in areducing gas such as H₂ (hydrogen) or CO (carbon monoxide) or mixedatmosphere of a reducing gas and an inert gas, the sputter etching maybe replaced with the annealing treatment. In the case of the annealingtreatment, loss of the insulative film 28 upon sputter etching orcharging damage to the gate oxide film 10 by electrons can be prevented.

[0111] Then, as shown in FIG. 28 and FIG. 29, a TaN (tantalum nitride)film, for example, as a barrier conductor film 22 A (first conductivefilm) is deposited above the wafer 1 by conducting reactive sputteringto a tantalum target in an argon/nitrogen mixed atmosphere. In FIG. 28,the barrier conductor film 22A is not illustrated in order for easyunderstanding of the step that forms the buried wirings in the wiringgrooves 21. The TaN film is deposited for improving the adhesion of a Cu(copper) film to be deposited in the sequent step and preventingdiffusion of Cu, and the thickness of the film is about 30 nm. Furtherin this Embodiment 1, while the TaN film is shown as an example of thebarrier conductor film 22A, it may be a metal film such as made of Ta(tantalum), a TiN (titanium nitride) film or a laminate film of a metalfilm and a nitride film. The barrier conductor film made of Ta or TaNhas more preferred adhesion with the Cu film than in the case of usingTiN. Further, when the barrier conductor film 22A is made of the TiNfilm, the surface of the TiN film can be sputter etched just beforeforming the Cu film as the subsequent step. By the sputter etching,water, molecules of oxygen, etc. adsorbed on the surface of the TiN filmcan be removed to improve the adhesion of the Cu film. This techniquehas a particularly large effect in a case of breaking vacuum to exposethe surface of the TiN film to atmospheric air after deposition therebyforming a copper film. This technique is not restricted to the TiN filmbut it is also effective in the TaN film although the difference ispresent in view of the effect.

[0112] Successively, a seed film, for example, made of a Cu film or acopper alloy film is deposited by a long distance sputtering method (notillustrated). In a case where the seed film is made of a copper alloyfilm, Cu is incorporated by about 80% by weight or more in the alloy.The thickness of the Cu film is about 1000 Å to 2000 Å, preferably,about 1500 Å at the surface of the barrier conductor film 22A except forthe inside of the wiring groove 21. While this embodiment shows anexample of using the long distance sputtering method for the depositionof the seed film, an ionizing sputtering for improving thedirectionality of the sputtering by ionizing sputter Cu atoms may alsobe used.

[0113] Successively, a Cu film, for example, is formed so as to bury thewiring grooves 21 over the entire surface of the wafer 1 deposited withthe seed film and the Cu film and the seed film are joined to constitutea conductive film 22B (first conductive film) The Cu film for buryingthe wiring grooves 21 is formed, for example, by an electrolytic platingmethod in which H₂SO₄ (sulfuric acid) with addition of 10% CuSO₄ (coppersulfate) and an additive for improving the Cu film coverage is used, forexample, as a plating solution. When the electrolytic plating method isused for the formation of the Cu film, since the growing rate of the Cufilm can be controlled electrically, coverage of the conductive film 22Bat the inside of the wiring grooves 21 can be improved. This embodimentshows a case of using the electrolytic plating method for the depositionof the conductive film 22B as an example but electroless plating methodmay also be used. Since application of voltage is not required in a caseof using the electroless plating method, damages attributable to theapplication of voltage can be decreased compared with the case of usingthe electrolytic plating method.

[0114] Further, by fluidizing the Cu film by the annealing treatmentsucceeding to the step of forming the conductive film 22B, the propertyof the conductive film 22B burying the wiring grooves 21 can also beimproved further.

[0115] Then, as shown in FIG. 30, the barrier conductor film 22A and theconductive film 22B on the edge of the wafer 1 are removed. The removingstep can be conducted by using the polishing drums 4A to 4C (refer toFIG. 4 to FIG. 7) in the same manner as the step of removing the siliconoxide film 2 and the silicon nitride film 3 on the edge of the wafer 1described previously. This can prevent the barrier conductor film 22Aand the conductive film 22B from remaining on the edge of the wafer 1.That is, it is possible to prevent the lowering for the yield of thesemiconductor integrated circuit device of Embodiment 1 by thedefoliation of the barrier conductor film 22A and the conductive film22B remained after polishing on the edge of the wafer 1, which aredeposited again on the wafer 1. Further, when Cu is diffused into thewafer 1, it lowers the gate withstand voltage of nMISQn. However, byremoving the conductive film 22B on the edge of the wafer 1 as describedabove, it is possible to prevent excessive Cu (conductive film 22B)deposited on the edge of the wafer 1 from diffusing into the wafer 1.

[0116] It has been described that the seed film is formed by thesputtering method. When the sputtering method is used, Cu atoms areimplanted also into the underlying insulation film 20. Therefore, in thestep of removing the barrier conductor film 22 a and the conductive film22B, it is also preferred to remove the underlying insulative film 20 byabout 50 nm. This can prevent diffusion of excess Cu (conductive film22B) deposited on the edge of the wafer 1 from diffusing into the wafer1 more reliably. Further, while Embodiment 1 shows a case of forming theconductive film 22B by the plating method as an example, it may beformed by using a sputtering method. Since the Cu atoms are implantedfurther into the insulative film 20 when the sputtering method is used,the step of removing the insulative film 20 below the conductive film22B on the edge of the wafer 1 constitutes a further effective means.

[0117] Then, as shown in FIG. 31 and FIG. 32, excessive barrierconductor film 22A and the conductive film 22B on the insulation film 20are polished, for example, by a CMP method with the surface of theinsulative film 20 in the chip region (refer to FIG. 14) being as apolishing end point, thereby leaving the barrier conductor film 22A andthe conductive film 22B in the wiring grooves 21 to form the wirings 22(first wirings).

[0118] Successively, after removing polishing abrasive grains and Cudeposited over the surface of the wafer 1 by a two step brush scrubbingcleaning, for example, using 0.1% aqueous ammonia solution and purifiedwater, a silicon nitride film is deposited on the buried wirings 22 andthe insulative film 20 to form a barrier insulative film 23A as shown inFIG. 33. For the deposition of the silicon nitride film, a plasma CVDmethod can be used, for example, and the film thickness is about 50 nm.The barrier insulative film 23A has a function of suppressing thediffusion of Cu as the conductive film 22B. This can prevent diffusionof copper into the barrier insulative film 22A, and the silicon oxidefilm 16, and the insulative film 20 and the insulative film formed onthe barrier insulative film 23A in the subsequent step and maintain theinsulation property thereof to enhance the reliability of thesemiconductor integrated circuit device. Further, the barrier insulativefilm 23A also functions as a etching stopper layer upon conductingetching in the subsequent step.

[0119] Then, an insulative film 23B of about 400 nm thickness isdeposited on the surface of the barrier insulative film 23A. Theinsulative film 23B is, for example, an SiOF film such as a CVD oxidefilm, for example, with addition of fluorine. In a case of using theSiOF film as the insulative film 23B, overall dielectric constant of thewirings in the semiconductor integrated circuit device can be lowered toimprove the wiring delay.

[0120] Then, a silicon nitride film is deposited on the surface of theinsulation film 23B, for example, by a plasma CVD method to deposit anetching stopper film 23C of about 50 nm thickness. When grooves or holesfor forming wirings are formed to the insulative film deposited on theetching stopper film 23C in the subsequent step the etching stopper film23 is used for avoiding that excessive digging damages the lower layeror deteriorates the fabrication dimensional accuracy.

[0121] Successively, an SiOF film, for example, is deposited on thesurface of the etching stopper film 23C to form an insulation film 23D,and the barrier insulation film 23A, the insulation film 23B, theetching stopper film 23C and the insulative film 23D are joined toconstitute an insulative film 23 (fourth insulative film). Theinsulative film 23D is deposited by a CVD method and the thickness is,for example, about 300 nm. The insulative film 23D has a function oflowering the overall dielectric constant of the wirings in thesemiconductor integrated circuit device like that the insulative film23B and can improve the wiring delay.

[0122] Subsequently, the insulative film 23 deposited on the edge of thewafer 1 may be removed by polishing the edge of the wafer 1 by using thepolishing drum 4A to 4C (refer to FIG. 4 to FIG. 7). This can eliminatethe worry that the insulative film 23 is defoliated on the edge of thewafer 1. That is, it is possible to prevent that the defoliatedinsulative film 23 forms obstacles that lower the yield of thesemiconductor integrated circuit device of Embodiment 1.

[0123] Then, after planarizing the insulative film 23D, for example, bypolishing the surface by a CMP method, connection holes 24A forconnecting the buried wirings 22 as the lower layer wirings to upperlayer wirings to be formed in the subsequent step are formed as shown inFIG. 34. For the connection holes 24A, a connection pattern is formed byforming a photoresist film of a shape identical with that of theconnection hole pattern for connection with the buried wirings 22 on theinsulative film 23D and conducting dry etching using the same as a mask.Successively, the photoresist film is removed, a photoresist film of ashape identical with that of the wiring groove pattern is formed by aphotolithographic step on the insulative film 23D and the wiring grooves24B are formed by dry etching using the photoresist film as a mask. Thestep of removing the insulative film 23 deposited on the edge of thewafer 1 may be conducted after the step of planarizing surface of theinsulative film 23D or after the step of forming the connection holes24A and the wiring grooves 24B.

[0124] Successively, sputter etching for removing the reaction layer onthe surface of the buried wirings 22 exposed at the bottom of theconnection holes 24A is conducted by the same step as the sputteretching step conducted for removing the reaction layer on the surface ofthe plugs 18 exposed at the bottom of the wiring grooves 21. The amountof the sputter etching is about 20 Å to 180 Å and, preferably, about 100Å0 being converted as the P-TEOS film.

[0125] Then, as shown in FIG. 35, a TaN film as the barrier conductorfilm 25A is deposited over the wafer 1 by the same step as the step ofdepositing the TaN film as the barrier conductor film 22A (refer to FIG.29). While Embodiment 1 describes the TaN film as an example of thebarrier conductor film 25A, it may be a metal film such as made of Ta, aTiN film or a stacked film of a metal film and nitride film like that inthe barrier conductor film 22A.

[0126] Successively, a Cu film or a copper alloy film as the seed filmlike that the seed film upon forming the conductive film 22B isdeposited, for example, by a long distance sputtering method or anionized sputtering method (not illustrated). Then, a Cu film, forexample, is deposited so as to bury the connection holes 24A and thewiring grooves 24B by the similar step as the step of depositing the Cufilm as the conductive film 22B that buries the wiring grooves 21 overthe entire surface of the wafer 1 deposited with the seed film, and theCu film and the seed film are joined to constitute a conductive film25B. After forming the conductive film 25B, the Cu film is fluidized bythe annealing treatment to further improve the burying property of theconductive film 25B into the connection holes 24A and the wiring grooves24B.

[0127] Then, the barrier conductor film 25A and the conductive film 25Bon the edge of the wafer 1 are removed by the similar step with the stepfor removing the barrier conductor film 22A and the conductive film 22Bon the edge of the wafer 1 (refer to FIG. 30). This can prevent thelowering of the yield of the semiconductor integrated circuit device ofEmbodiment 1 by the defoliation of the barrier conductor film 25A andthe conductive film 25B remaining after polishing on the edge of thewafer 1 after the CMP step to be described later, which are depositedagain to the wafer 1. Further, when Cu is diffused into the wafer 1, itlowers the gate withstand voltage of nMISQn. However, when theconductive film 25B on the edge of the wafer 1 is removed, diffusion ofthe excess Cu (conductive film 25B) deposited on the edge of the wafer 1can be prevented from diffusing into the wafer 1.

[0128] Further, since the Cu atoms have been implanted also into theunderlying insulative film 23D upon deposition of the seed film, it ispreferred to remove also the underlying insulation film by about 50 nm.This can prevent excessive Cu (conductive film 25B) deposited on theedge of the wafer 1 from diffusing into the wafer 1 further reliably.Further, Embodiment 1 describes a case of forming the conductive film25B by the plating method as an example but it may be formed by using asputtering method. When the sputtering method is used, since Cu atomsare further implanted into the insulation film 23D, the step of removingthe insulative film 23D below the conductive film 25B on the edge of thewafer 1 can constitute a further effective means.

[0129] Then, the excessive barrier conductive film 25A and theconductive film 25B on the insulative film 23D are removed leaving thebarrier conductor film 25A and the conductive film 25B in the inside ofthe connection holes 24A and the wiring grooves 24B to form the buriedwirings 25. The barrier conductor film 25A and the conductive film 25are removed, for example, by polishing using a CMP method.

[0130] Successively, the polishing abrasive grains and Cu deposited overthe surface of the wafer 1 are removed by a two step brush scrubbingcleaning using, for example, 0.1% aqueous ammonia solution and purifiedwater to fabricate a semiconductor integrated circuit device of thisembodiment. Wirings may also be formed in a more layer structure abovethe buried wirings 26 by the similar steps with those explained withreference FIG. 33 to FIG. 35.

EMBODIMENT 2

[0131] In Embodiment 2, thin films to be removed on the edge of thewafer are patterned before the removing step. Other components andfabrication steps are identical with those of Embodiment 1 describedabove.

[0132] The fabrication method of the semiconductor integrated circuitdevice of Embodiment 2 include the same steps up to those as have beenexplained for Embodiment 1 with reference to FIG. 1 and FIG. 2.

[0133] Then, as shown in FIG. 36, after coating the photoresist film 5above the wafer 1, the photoresist film 5 is patterned by exposure usinga mask. Successively, as shown in FIG. 37, the silicon nitride film 3and the silicon oxide film 2 in the device isolation regions are removedby dry etching using the photoresist film 5 as a mask. Successively,grooves 6 each of about 350 nm depth are formed above the wafer 1 in thedevice isolation region by dry etching using the silicon nitride films 3as a mask.

[0134] Then, as shown in FIG. 38, the wafer 1 is heat treated at about1000° C. to form the thin silicon oxide film 7 of about 10 nm thicknessto the inner wall of the grooves 6 for removing the damages layer formedon the inner wall of the grooves 6 by etching. Successively, the siliconoxide film 8 of about 380 nm thickness is deposited above the wafer 1 bya CVD method and then the wafer 1 is heat treated to densify (sinter)the silicon oxide film 8 in order to improve the film quality of thesilicon oxide film 8.

[0135] Then, as shown in FIG. 39, the silicon oxide film 8 is polishedby a CMP method using the silicon nitride film 3 as a stopper leavingthe film at the inside of the grooves 6 to form a device isolationgroove planarized at the surface. Successively, as shown in FIG. 40, thesilicon oxide film 8 on the edge of the wafer 1 is removed till thesilicon nitride film 3 therebelow is exposed by using the polishingdrums 4A to 4C explained with reference to FIG. 4 to FIG. 7 inEmbodiment 1 described previously.

[0136] Successively, as shown in FIG. 41, the silicon nitride film 3 andthe silicon oxide film 2 remaining above the wafer 1 are removed by wetetching using hot phosphoric acid as shown in FIG. 41. In this case,since the surface of the silicon oxide film 3 is exposed on the edge ofthe wafer 1, the silicon nitride film 3 and the silicon oxide film 2 canremoved over the entire surface of the wafer 1. This can prevent thatthe silicon nitride film 3 and the silicon oxide film 2 are defoliatedto form obstacles in the subsequent cleaning step.

[0137] Then, after passing the identical steps with those explained withreference to FIG. 23 to FIG. 29 in Embodiment 1 described previously,the excessive barrier conductor film 22A (refer to FIG. 29) andconductive film 22B (refer to FIG. 29) on the insulative film 20 areremoved by polishing, for example, using a CMP method, leaving thebarrier conductive film 22A and the conductive film 22B into the wiringgrooves 21 to form buried wirings 22 as shown in FIG. 42.

[0138] As shown in FIG. 43, the barrier conductor film 22A and theconductive film 22B on the edge of the wafer 1 are removed by using thepolishing drums 4A to 4C explained with reference to FIG. 4 to FIG. 7 inEmbodiment 1 described previously. This can prevent the barrierconductive film 22A and the conductive film 22B from remaining on thewafer edge of the wafer 1. That is, it can prevent lowering of the yieldof the semiconductor integrated circuit device of Embodiment 2 bydefoliation of the barrier conductive film 22 a and the conductive film22B remained after polishing on the edge of the wafer 1, which aredeposited again to the wafer 1.

[0139] Subsequently, a semiconductor integrated circuit device ofEmbodiment 2 is fabricated by the steps identical with those explainedwith reference to FIG. 33 to FIG. 35 in Embodiment 1. Embodiment 1describes a case of removing the insulative film 23 deposited on theedge of the wafer 1 (refer to FIG. 33) before planarizing the surface ofthe insulative film 23D (refer to FIG. 33) as an example, but the stepof removing the insulative film 23B may be conducted after forming theconnection holes 24A and the wiring grooves 24B or before depositing thebarrier conductor film 25A (refer to FIG. 35). Further, Embodiment 1describes a case of removing the insulative film 23 deposited on theedge of the wafer 1 (refer to FIG. 33) before the step of removing theexcessive barrier conductor film 25A and conductive film 25B on theinsulative film 23D (refer to FIG. 35) by the CMP method but the stepmay be conducted after removing the barrier conductor film 25A and theconductive film 25B (refer to FIG. 35) by the CMP method.

EMBODIMENT 3

[0140] In the fabrication method of a semiconductor integrated circuitdevice of Embodiment 3, this invention is applied to a fabricationmethod of a semiconductor integrated circuit device having wirings, forexample, formed of Al (aluminum) or aluminum alloy.

[0141] The fabrication method of the semiconductor integrated circuitdevice of Embodiment 3 include the same steps explained with referenceto FIG. 1 to FIG. 25 in Embodiment 1.

[0142] Subsequently, as shown in FIG. 44 and FIG. 45, a conductive film22C (first conductive film) such as TiN is deposited above the wafer 1by a sputtering method. In FIG. 44, the conductive film 22C is notillustrated for easy understanding of the step for forming wirings onthe silicon oxide film 16.

[0143] Successively, a conductive film 22D, for example, made of Al(first conductive film) is deposited on the surface of the conductivefilm 22C. Further successively, a conductive film 22E, for example, madeof TiN is deposited on the surface of the conductive film 22D. Theconductive film 22E has a function of preventing random reflection oflight when the conductive film 22C, the conductive film 22D and theconductive film 22E (first conductive film) are patterned by aphotolithographic step. Deposition of the conductive film 22D and theconductive film 22E are conducted, for example, by a sputtering method.

[0144] Then, as shown in FIG. 46, the conductive films 22C to 22E on theedge of the wafer 1 are removed by using the polishing drum 4A to 4cexplained with reference to FIG. 4 to FIG. 7 in Embodiment 1 describedpreviously. This can prevent the conductive films 22C to 22E fromremaining on the edge of the wafer 1. That is, it is possible to preventlowering of the yield of the semiconductor integrated circuit device ofEmbodiment 3 by the defoliation of the conductive film 22C to 22Eremaining after polishing on the edge of the wafer 1, which aredeposited again to the wafer 1.

[0145] Then, as shown in FIG. 47 and FIG. 48, the conductive films 22Cto 22E are fabricated by using a dry etching technique to form wirings22F to fabricate a semiconductor integrated circuit device of Embodiment3. Embodiment 3 describes a case of removing the conductive films 22C to22E deposited on the edge of the wafer 1 before forming the wirings 22Fas an example, but the step of removing the conductive films 22C to 22Emay be conducted after forming the wirings 22F.

[0146] The inventions accomplished by the present inventors have beenexplained concretely with reference to the embodiments of the inventionbut it will be apparent that the invention is not restricted to theembodiments described above but may be variously modified within a scopenot departing the gist thereof.

[0147] For example, the embodiments described above show a case wherethree polishing drums are used for polishing the edge of the wafer butmore than three polishing drums may also be used.

[0148] Further, the embodiments described above show a case of polishingthe edge of the wafer by using the polishing drums, it may be polishedby using a grinding wheel profiled to the edge of the wafer, or apolishing tape manufactured by embedding a slurry into an organic resin.

[0149] Further, the embodiments described above show an example of afabrication method of a semiconductor circuit device in which nMIS isformed to the p-well, it may be applicable also to a fabrication methodof a semiconductor integrated circuit device in which pMIS is formed toan n-well.

[0150] Among the inventions disclosed in the present application,effects obtained by typical ones are briefly explained as below.

[0151] (1) Since thin films formed on the edge of the wafer are removed,it can prevent lowering of yield of the semiconductor integrated circuitdevice caused by defoliation of the thin films, which are depositedagain to the wafer.

[0152] (2) Since the angle at which the wafer and the polishing drum arein contact with each other and the optimal polishing speed can be set inaccordance with the shape of the edge of the wafer and the depositionstate of the thin films as a target to be removed on the edge of thewafer, the thin films can be removed over the entire area on the edge ofthe wafer.

What is claimed is:
 1. A fabrication method of a semiconductorintegrated circuit device comprising the steps of: (a) forming a firstinsulative film of a single layer or a stacked layer on a surface of asemiconductor wafer; (b) removing the first insulative film on an edgeof the semiconductor wafer; (c) patterning the first insulative filmafter the step (b); (d) etching the semiconductor wafer by using thefirst insulative film as a mask after the step (c); (e) forming a secondinsulative film on the semiconductor wafer including a portion on thefirst insulative film after the step (d); and (f) mechanically andchemically polishing a surface of the second insulative film, therebyplanarizing the surface thereof.
 2. A fabrication method of asemiconductor integrated circuit device according to claim 1, whereinthe step (b) is conducted by polishing with a polishing means using aslurry or a grinding wheel.
 3. A fabrication method of a semiconductorintegrated circuit device according to claim 2, wherein the polishingmeans has plural polishing drums in which each of the plural polishingdrums are in contact with the edge of the semiconductor wafer in aregion different from each other and the angle of contact changes inaccordance with the shape of the edge of the semiconductor wafer.
 4. Afabrication method of a semiconductor integrated circuit deviceaccording to claim 1, wherein the step (b) is conducted by dry etchingor wet etching.
 5. A fabrication method of a semiconductor integratedcircuit device comprising the steps of: (a) forming a first insulativefilm of a single layer or a stacked layer on a surface of asemiconductor wafer; (b) patterning the first insulative film; (c)etching the semiconductor wafer by using the first insulative film as amask after the step (b); (d) forming a second insulative film on thesemiconductor wafer including a portion on the first insulative filmafter the step (c); (e) mechanically and chemically polishing a surfaceof the second insulative film, thereby planarizing the surface thereof;and (f) polishing the second insulative film on an edge of thesemiconductor wafer with the first insulative film being as a polishingend point after the step (e).
 6. A fabrication method of a semiconductorintegrated circuit device according to claim 5, wherein the step (f) isconducted by polishing with a polishing means using a slurry or agrinding wheel.
 7. A fabrication method of a semiconductor integratedcircuit device according to claim 6, wherein the polishing means hasplural polishing drums in which each of the plural polishing drums arein contact with the edge of the semiconductor wafer in a regiondifferent from each other and the angle of contact changes in accordancewith the shape of the edge of the semiconductor wafer.
 8. A fabricationmethod of a semiconductor integrated circuit device according to claim5, wherein the step (f) is conducted by dry etching or wet etching.
 9. Afabrication method of a semiconductor integrated circuit devicecomprising the steps of: (a) forming a third insulative film on asurface of a semiconductor wafer; (b) patterning the third insulativefilm; (c) forming a first conductive film over the semiconductor waferincluding a portion on the third insulative film; (d) removing the firstconductive film on an edge of the semiconductor wafer after the step(c); and (e) mechanically or chemically polishing the first conductivefilm with a surface of the third insulative film on a semiconductor chipobtainable region of the semiconductor wafer being as a polishing endpoint.
 10. A fabrication method of a semiconductor integrated circuitdevice according to claim 9, wherein the step (f) is conducted bypolishing with a polishing means using a slurry or a grinding wheel. 11.A fabrication method of a semiconductor integrated circuit deviceaccording to claim 10, wherein the polishing means has plural polishingdrums in which each of the plural polishing drums are in contact withthe edge of the semiconductor wafer in a region different from eachother and the angle of contact changes in accordance with the shape ofthe edge of the semiconductor wafer.
 12. A fabrication method of asemiconductor integrated circuit device according to claim 9, whereinthe step (d) is conducted by dry etching or wet etching.
 13. Afabrication method of a semiconductor integrated circuit deviceaccording to claim 9, wherein the third insulative film on the edge ofthe semiconductor wafer is also removed by a predetermined thickness inthe step (d) in a case where the first conductive film is a copper filmor a copper alloy film.
 14. A fabrication method of a semiconductorintegrated circuit device comprising the steps of: (a) forming a thirdinsulative film on a surface of a semiconductor wafer; (b) patterningthe third insulative film; (c) forming a first conductive film over thesemiconductor wafer including a portion on the third insulative filmafter the step (b); (d) mechanically or chemically polishing the firstconductive film with the surface of the third insulative film on thesemiconductor chip obtainable region of the semiconductor wafer being asa polishing end point; and (e) removing the first conductive film on theedge of the semiconductor wafer after the step (d).
 15. A fabricationmethod of a semiconductor integrated circuit device according to claim14, wherein the step (e) is conducted by polishing with a polishingmeans using a slurry or a grinding wheel.
 16. A fabrication method of asemiconductor integrated circuit device according to claim 15, whereinthe polishing means has plural polishing drums in which each of theplural polishing drums are in contact with the edge of the semiconductorwafer in a region different from each other and the angle of contactchanges in accordance with the shape of the edge of the semiconductorwafer.
 17. A fabrication method of a semiconductor integrated circuitdevice according to claim 14, wherein the step (e) is conducted by dryetching or wet etching.
 18. A fabrication method of a semiconductorintegrated circuit device according to claim 14, wherein the thirdinsulative film on the edge of the wafer is also removed bypredetermined thickness in the step (e) in a case where the firstconductive film is a copper film or a copper alloy film.
 19. Afabrication method of a semiconductor integrated circuit deviceincluding steps of: (a) forming a first conductive film on asemiconductor wafer; (b) removing the first conductive film on an edgeof the semiconductor wafer with a polishing means using a slurry or aabrasive wheel; and (c) patterning the first conductive film, therebyforming wirings after the step (b).
 20. A fabrication method of asemiconductor integrated circuit device comprising the steps of: (a)forming a first conductive film on a semiconductor wafer; (b) patterningthe first conductive film, thereby forming wirings; and (c) removing thefirst conductive film on an edge of the semiconductor wafer with apolishing means using a slurry or an abrasive wheel after the step (b).21. A fabrication method of a semiconductor integrated circuit devicecomprising the steps of: (a) forming a first conductive film on asemiconductor wafer; (b) patterning the first conductive film, therebyforming first wirings; (c) forming a fourth insulative film over thesemiconductor wafer including a portion on the first wirings; (d)removing the fourth insulative film on an edge of the semiconductorwafer; and (e) mechanically and chemically polishing the surface of thefourth insulative film, thereby planarizing the surface thereof afterthe step (d).
 22. A fabrication method of a semiconductor integratedcircuit device according to claim 21, wherein the step (d) is conductedby polishing with a polishing means using a slurry or an abrasive wheel.23. A fabrication method of a semiconductor integrated circuit deviceaccording to claim 22, wherein the polishing means includes pluralpolishing drums, each of the plural polishing drums is in contact withthe edge of the semiconductor wafer at a region different from eachother and the angle of contact thereof changes depending on the shape ofthe edge of the semiconductor wafer.
 24. A fabrication method of asemiconductor integrated circuit device according to claim 21, whereinthe step (d) is conducted by dry etching or wet etching.
 25. Afabrication method of a semiconductor integrated circuit devicecomprising the steps of: (a) forming a first conductive film on asemiconductor wafer; (b) patterning the first conductive film, therebyforming first wirings; (c) forming a fourth insulative film over thesemiconductor wafer including a portion on the first wirings; (d)mechanically and chemically polishing a surface of the fourth insulativefilm, thereby planarizing the surface thereof; and (e) removing thefourth insulative film on the edge of the semiconductor wafer after thestep (d).
 26. A fabrication method of a semiconductor integrated circuitdevice according to claim 25, wherein the step (e) conducting polishingby a Polishing means using a slurry or an abrasive wheel.
 27. Afabrication method of a semiconductor integrated circuit deviceaccording to claim 26, wherein the polishing means includes pluralpolishing drums, each of the plural polishing drums is in contact withthe edge of the semiconductor wafer at a region different from eachother and the angle of contact thereof changes depending on the shape ofthe edge of the semiconductor wafer.
 28. A fabrication method of asemiconductor integrated circuit device according to claim 25, whereinthe step (e) is conducted by dry etching or wet etching.
 29. Afabrication method of a semiconductor integrated circuit devicecomprising the steps of: (a) forming a single layer or stacked layer ofa first insulation film on a surface of a semiconductor wafer; (b)removing the first insulative film on an edge of the semiconductorwafer; (c) patterning the insulative film after the step (b); (d)etching the semiconductor wafer using the first insulative film as amask after the step (c); (e) forming a second insulative film over thesemiconductor wafer including a portion on the first insulative filmafter the step (d); (f) mechanically and chemically polishing a surfaceof the second insulative film, thereby planarizing surface thereof; (g)forming a third insulative film over the semiconductor wafer after thestep (f); (h) removing the third insulative film on the edge of thesemiconductor wafer; and (i) mechanically and chemically polishing asurface of the third insulative film, thereby planarizing the surfacethereof after the step (h).
 30. A fabrication method of a semiconductorintegrated circuit device comprising the steps of: (a) forming a singlelayer or stacked layer of a first insulation film on a surface of asemiconductor wafer; (b) removing the first insulative film on an edgeof the semiconductor wafer; (c) patterning the insulative film after thestep (b); (d) etching the semiconductor wafer by using the firstinsulative film as a mask after the step (c); (e) forming a secondinsulative film over the semiconductor wafer including a portion on thefirst insulative film after the step (d); (f) mechanically andchemically polishing a surface of the second insulative film, therebyplanarizing the surface thereof; (g) forming a third insulative filmover the semiconductor wafer after the step (f); (h) mechanically andchemically polishing the surface of the third insulative film, therebyplanarizing surface thereof; and (i) removing the third insulative filmon the edge of the semiconductor wafer after the step (h).
 31. Afabrication method of a semiconductor integrated circuit devicecomprising the steps of: (a) forming a single layer or a stacked layerof a first insulative film on a surface of a semiconductor wafer; (b)patterning the first insulative film; (c) etching the semiconductorwafer by using the first insulative film as a mask after the step (b);(d) forming a second insulative film over the semiconductor waferincluding a portion on the first insulative film after the step (c); (e)mechanically and chemically polishing a surface of the second insulativefilm, thereby planarizing the surface thereof; (f) polishing the secondinsulative film on the edge of the semiconductor wafer with the firstinsulative film being as a polishing end point after the step (e); (g)forming a third insulative film over the semiconductor wafer after thestep (f); (h) removing the third insulative film on an edge of thesemiconductor wafer; and (i) mechanically and chemically polishing asurface of the insulative film, thereby planarizing the surface thereofafter the step (h).
 32. A fabrication method of a semiconductorintegrated circuit device comprising the steps of: (a) forming a singlelayer or a stacked layer of a first insulative film on a surface of asemiconductor wafer; (b) patterning the first insulative film; (c)etching the semiconductor wafer by using the first insulative film as amask after the step (b); (d) forming a second insulative film over thesemiconductor wafer including a portion on the first insulative filmafter the step (c); (e) mechanically and chemically polishing a surfaceof the second insulative film, thereby planarizing the surface thereof;(f) polishing the second insulative film on the edge of thesemiconductor wafer with the first insulative film being as a polishingend point after the step (e); (g) forming a third insulative film overthe semiconductor wafer after the step (f); (h) mechanically andchemically polishing a surface of the third insulative film, therebyplanarizing the surface thereof; and (i) removing the third insulativefilm on an edge of the semiconductor wafer after the step (h).